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RHF1201
Rad-hard 12-bit 0.5 to 50 Msps A/D converter
Features

SO-48 package
Wide sampling range: 0.5Msps to 50Msps OptimwattTM adaptive power: 44mW @ 0.5Msps, 100mW @ 50Msps Input range: 2 Vpp differential SFDR up to 75dB @ FS = 50Msps, Fin = 15MHz 2.5V / 3.3V compatible digital I/O Built-in reference voltage with external bias capability Hermetic package Rad-hard: 300 kRad(Si) TID Failure immune (SEFI) and latchup immune (SEL) up to 120 MeV-cm2/mg at 2.7V and 125C Qml-V qualified, smd 5962-05217
24 25
Pin connections (top view)
1 48
Applications

Digital communication satellites Space data acquisition systems Aerospace instrumentation Nuclear and high-energy physics
Specifically designed for optimizing power consumption, the RHF1201 can dissipate as little as 100mW at 50Msps, while maintaining a high level of performance. It integrates a proprietary track-and-hold structure to ensure IF-sampling applications up to 150 MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. A tri-state capability is available on the outputs to allow common bus sharing. Output data can be coded in two different formats. A Data Ready signal which is raised when the data is valid on the output can be used for synchronization purposes. The RHF1201 is available in -55 C to +125 C temperature range, in a small 48-pin hermetic SO-48 package.
Description
The RHF1201 is a 12-bit 50MHz maximum sampling frequency analog to digital converter using pure (ELDRS-free) CMOS 0.25m technology combining high performance, radiation robustness and very low power consumption. The RHF1201 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 10.3 effective bits at FS = 50Msps, and Fin = 15MHz.
June 2007
Rev 2
1/18
www.st.com 18
Contents
RHF1201
Contents
1 2 3 4 5 6 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 6 Electrical characteristics (unchanged after 300kRad) . . . . . . . . . . . . . . 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 7.2 RHF1201 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2.1 7.2.2 7.2.3 Differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IF-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.3
Reference connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3.1 7.3.2 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.4 7.5 7.6
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 10 11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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RHF1201
Block diagram
1
Block diagram
Figure 1. Block diagram
+2.5V +2.5V/3.3V VREFP
GNDA VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM DFSB Sequencer-phase shifting CLK SRC OEB
Timing
Digital data correction DR DO Buffers TO D11 OR GND
2
Pin connections
Figure 2. Pin connections (top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
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Pin descriptions
RHF1201
3
Table 1.
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin descriptions
Pin descriptions
Name
GNDBI GNDBE VCCBE
Description
Digital buffer ground Digital buffer ground Digital buffer power supply NC NC
Observation
0V 0V 2.5 V/3.3 V Non connected Non connected CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) Non connected Non connected 2.5 V/3.3 V 0V 2.5 V
Pin
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Name
SRC OEB DFSB AVCC AVCC AGND IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
Description
Slew rate control input Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground Analog bias current input Top voltage reference Bottom voltage reference Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Digital ground
Observation
2.5 V/3.3 V CMOS input 2.5 V/3.3 V CMOS input 2.5 V/3.3 V CMOS input 2.5 V 2.5 V 0V
OR D11(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) DR
Out Of Range output Most Significant Bit output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Data Ready output NC NC
1V 0V 0V 1 Vpp 0V 1 Vpp 0V 0.5 V 0V 2.5 V 2.5 V 2.5 V 2.5 V 0V 2.5 V compatible CMOS input 0V 0V
DVCC DVCC
DGND CLK DGND DGND
VCCBE GNDBE VCCBI
Digital Buffer power supply Digital Buffer ground Digital Buffer power supply
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RHF1201
Timing characteristics
4
Timing characteristics
Table 2.
Symbol FS Tck DC TC1 TC2 Tod Tpd Tdr Ton Toff
Timing table
Parameter Sampling frequency Sampling clock cycle Clock duty cycle Clock pulse width (high) Clock pulse width (low) Data output delay (fall of clock to data valid) Data pipeline delay Data ready delay after data change Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state SRC = 0 5 pF load capacitance 10 pF load capacitance FS = 45 Msps Test conditions Min 0.5 20 45 10 8 4 5.5 5 5.5 0.5 1 1 2.8 5.7 2 4.3 3 3 50 Typ Max 50 2000 65 1800 1800 6 5.5 Unit MHz ns % ns ns ns cycles cycles ns ns ns ns ns ns
TrD
Data rising time SRC = 1 5pF load capacitance SRC = 0 5pF load capacitance
TfD
Data falling time SRC = 1 5pF load capacitance
Figure 3.
Timing diagram
N+2 N+1 N+3 N+4
N N-3 N-2 N-1
N+5 N+6
CLK
Tdr
OEB Tod DATA OUT N-9 N-8 N-7 N-6
Tpd + Tod
Toff N-5 N-4 N-3
Ton N-1 N
DR
HZ state
5/18
Absolute maximum ratings and operating conditions
RHF1201
5
Absolute maximum ratings and operating conditions
Table 3.
Symbol AVCC DVCC VCCBI VCCBE IDout Tstg Rthjc ESD
Absolute maximum ratings
Parameter Analog supply voltage(1) Digital supply voltage
(1) (1)
Values 0 to 3.3 0 to 3.3 0 to 3.3 0 to 3.6 -100 to 100 -65 to +150 22 2
Unit V V V V mA C C/W kV
Digital buffer supply voltage
Digital buffer supply voltage(1) Digital output current Storage temperature Junction - case thermal resistance Electrostatic discharge - HBM
1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3 V or VCC +0.3 V.
Table 4.
Symbol AVCC DVCC VCCBI VCCBE VREFP VREFM
Operating conditions
Parameter Analog supply voltage Digital supply voltage Digital internal buffer supply Digital output buffer supply Forced top voltage reference Bottom internal reference voltage Test conditions Min 2.3 2.3 2.3 2.3 0.5 0 Typ 2.5 2.5 2.5 2.5 1 0 Max 2.7 2.7 2.7 3.4 AVCC 0.5 Unit V V V V V V
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RHF1201
Electrical characteristics (unchanged after 300kRad)
6
Electrical characteristics (unchanged after 300kRad)
Test conditions, unless otherwise specified are: AVCC = DVCC = VCCB = 2.5 V, FS = 50 Msps, Fin = 2 MHz, VIN @ -1 dBSF, VREFP = Internal, VREFM = 0 V, Tamb = 25 C
Table 5.
Symbol VIN-VINB Cin Rin ERB
Analog inputs
Parameter Full scale reference voltage Input capacitance Input resistance Effective resolution bandwidth(1) 95 MHz Test conditions Min Typ 2.0 7.0 Max Unit Vpp pF
1. See Section 8: Definitions of specified parameters on page 14 for more information.
Table 6.
Symbol
Reference voltage
Parameter Test conditions AVCC from 2.3V to 2.7V Tmin = -55 C to Tmax = 125 C(1) AVCC=2.3 V to AVCC=2.7 V Tmin = -55 C to Tmax = 125 C(1) VREFP Tmin = -55 C to Tmax = 125 C(1) VINCM Tmin = -55 C to Tmax = 125 C(1) Min Typ Max Unit
VREFP
Top internal reference voltage
0.82
0.95
1.16
V
VINCM
Input common mode voltage
0.43
052
0.67
V
0.12
mV/C
TempCo
Temperature coefficients
0.12
mV/C
1. Not fully tested over the temperature range. Guaranteed by sampling.
Table 7.
Symbol Clock input VIL VIH
Digital inputs and outputs
Parameter Test conditions Min Typ Max Unit
Logic "0" voltage Logic "1" voltage 2.0
0 2.5
0.8
V V
Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage 0.75 VCCBE 0 VCCBE 0.25 VCCBE V V
7/18
Electrical characteristics (unchanged after 300kRad) Table 7.
Symbol Digital outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage High impedance leakage current Output load capacitance IOL = -1mA IOH = 1mA OEB set to VIH VCCBE - 0.2 -15 15 15 0 0.2
RHF1201
Digital inputs and outputs (continued)
Parameter Test conditions Min Typ Max Unit
V V A pF
Table 8.
Symbol OE DNL INL -
Accuracy
Parameter Offset error Differential non linearity(1) Integral non linearity(1) Monotonicity and no missing codes Test conditions Fin = 2 MHz, VIN @ +1 dBFS Fin = 2 MHz, VIN @ +1 dBFS Fin = 2 MHz, VIN @ +1 dBFS Min Typ 0.3 0.5 1.7 Guaranteed Max Unit % LSB LSB
1. See Section 8: Definitions of specified parameters on page 14 for more information.
Table 9.
Symbol
Dynamic characteristics
Parameter(1) Test conditions(2) Fin = 15 MHz Min Typ -75 -70 -57 59 63 60 59 -76 -72 -58 59 63 60 56.5 9.7 10.3 9.5 9.1 dB bits bits dB -64 dB dB dBc dB dB Max -63 Unit dBc
SFDR
Spurious free dynamic range
Fin = 95 MHz Fin = 145 MHz Fin = 15 MHz
SNR
Signal to noise ratio
Fin = 95 MHz Fin = 145 MHz Fin = 15 MHz
THD
Total harmonics distortion
Fin = 95 MHz Fin = 145 MHz Fin = 15 MHz
SINAD
Signal to noise and distortion ratio
Fin = 95 MHz Fin = 145 MHz Fin = 15 MHz
ENOB
Effective number of bits
Fin = 95 MHz Fin = 145 MHz
1. See Section 8: Definitions of specified parameters on page 14 for more information. 2. VREFP = 1 V with external supply.
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RHF1201
Application information
7
Application information
The RHF1201 is a high speed analog to digital converter based on a pipeline architecture and a 0.25 m CMOS process to achieve the best performance in terms of linearity and power consumption. The pipeline structure consists of 11 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Signal input is sampled on the rising edge of the clock. The first 10 stages of the conversion include at each stage, an analog to digital converter, a digital to analog converter, a Sample and Hold, and an amplifier with a gain of 2. A 1.5 bit conversion resolution is also performed at each stage. The final stage is simply a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay caused by the conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple at each stage. The corrected data is output through the digital buffers. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level.
7.1
RHF1201 operating modes
Extra functionalities are provided to simplify the application board as much as possible. The operation modes offered by the RHF1201 are described in the following table. Table 10. RHF1201 operating modes
Inputs Analog input differential level (VIN-VINB) -RANGE RANGE> (VIN-VINB) -RANGE RANGE> > > (VIN-VINB) > > (VIN-VINB) X X X RANGE (VIN-VINB) >-RANGE RANGE (VIN-VINB) >-RANGE DFSB H H H L L L X X X OEB L L L L L L H X X SRC X X X X X X X H L OR H H L H H L HZ X X DR CLK CLK CLK CLK CLK CLK HZ CLK CLK Outputs Most significant bit (MSB) D11 D11 D11 D11 Complemented D11 Complemented D11 Complemented HZ Low slew rate High slew rate
Data format select (DFSB)
When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding.
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Application information
RHF1201
Output enable (OEB)
When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This mechanism allows the chip select of the device. Figure 3: Timing diagram on page 5 summarizes this functionality.
Slew rate control (SRC)
When set to high level (VIH), all digital output currents are limited to a clamp value so that digital noise power is reduced to the minimum. When set to low level (VIL), the output edges are twice as fast.
Out of range (OR)
This function is implemented on the output stage in order to set an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data at '0' or all the data at '1'. It sets an output signal OR which is in low level state (VOL) when the data stays within the range, or in high level state (VOH) when the data is out of range.
Data ready (DR)
The Data Ready output is an image of the clock being synchronized on the output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of the measurement equipment or of the controlling DSP. As all other digital outputs, DR goes into high impedance state when OEB is set to high level as shown in Figure 3: Timing diagram on page 5.
7.2
7.2.1
Driving the analog input
Differential inputs
The RHF1201is designed to obtain optimum performance when driven on differential inputs. An RF transformer is an efficient way of achieving this high performance. Figure 4: Differential input configuration describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set close to 0.5V. The INCM is de-coupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1 Vpp amplitude input signal, so the resulting differential amplitude is 2 Vpp.
10/18
RHF1201 Figure 4. Differential input configuration
Analog source ADT1-1 1:1 VIN
50 10-100pF
Application information
RHF1201
VINB INCM
330pF
10nF
470nF
7.2.2
Single-ended input configuration
Some applications may require a single-ended input which is easily achieved with the configuration shown in Figure 5: Single-ended input configuration. The lack of accurate differential driving with its common-mode noise and even harmonics cancellation advantages can degrade the rated RHF1201 performance. It is then recommended to use a well de-coupled DC reference to bias the RHF1201 inputs. In this case, one can use an AC-coupled analog input and set the DC analog level with high value (10 k to 100 k) resistor connected to a proper DC source. The internal references INCM (0.52 V) or REFP (1 V) can be used as proper DC sources. Using 1 V DC with a single signal of 2 Vpp input amplitude gives better SNR performance. Figure 5. Single-ended input configuration
Signal source
10nF
VIN
50 10-100k
RHF1201
VINB
330pF
10nF
470nF
DC source or REFP
7.2.3
IF-sampling
The RHF1201 is specifically designed to meet sampling requirements for intermediate frequency input signals. In particular, the Track-and-Hold in the first stage of the pipeline is designed to minimize the linearity limitations as analog frequency increases.This is achieved by making the input impedance independent from the input frequency. As a result, the RHF1201 can maintain high performance up to an analog frequency of 150 MHz.
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Application information
RHF1201
7.3
7.3.1
Reference connection
Internal reference
In the standard configuration, the ADC is biased with the internal reference voltage. The VREFM pin is connected to Analog Ground while VREFP is internally set to a voltage close to 1.0 V. It is recommended to de-couple the VREFP in order to minimize low and high frequency noise. Refer to Figure 6: Internal reference setting for the schematics. Figure 6. Internal reference setting
~1V VIN VREFP
330pF 10nF 470nF
RHF1201
VINB VREFM
7.3.2
External reference
It is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced temperature behavior. In this case, the amplitude of the external voltage must be at least equal to the internal one (1.0 V). You can use an external voltage reference with the configuration shown in Figure 7: External reference setting to obtain optimum performance. Figure 7. External reference setting
1k
330pF
10nF 470nF
VCCA VREFP VIN RHF1201 VINB VREFM
external reference
This can be very helpful in multichannel applications for example to maintain a good matching along the sampling frequency range.
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RHF1201
Application information
7.4
Clock input
The quality of your converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended. Further points to consider in your implementation are:

The input signal must be square-shaped with sharp edges of less than 1 ns. At 45 Msps, the duty cycle must be between 45% and 65%; in any case, the high level duration of Clock must be longer than 10 ns. The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output. When powered-on, the circuit needs several clock periods to reach its normal operating conditions.
7.5
Power consumption optimization
The internal architecture of the RHF1201 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an External Rpol resistor is placed between the IPOL pin and the analog Ground. Therefore, the total dissipation can be adjusted across all the sampling range 0.5 Msps to 50 Msps to fulfil the requirements of applications where power saving is a must. For low sampling frequency, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance. Table 11 sums up the relevant data. Table 11.
FS (Msps) Rpol (k) Optimized power (mW)
Total power consumption optimization depending on Rpol value
0.85 100 44 1.7 70 47 13.6 35 60 45 24 93 50 18 100
7.6
Layout precautions
Use of dedicated ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital output part is mandatory to prevent noise from coupling onto the input signal. Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. Keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. Choose component sizes as small as possible (SMD).

13/18
Definitions of specified parameters
RHF1201
8
Definitions of specified parameters
Static parameters
Static measurements are performed using the histograms method on a 2 MHz input signal, sampled at 50 Msps, which is high enough to fully characterize the test frequency response. The input level is +1 dBFS to saturate the signal.
Differential non linearity (DNL)
The average deviation of any output code width from the ideal code width of 1 LSB.
Integral non linearity (INL)
An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition.
Dynamic parameters
Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 50 Msps.
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/ 2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB.
Signal to noise and distortion ratio (SINAD)
Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula: SINAD = 6.02 x ENOB + 1.76 dB. When the applied signal is not full scale (FS), but has an amplitude A0, the SINAD expression becomes: SINAD = 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits.
14/18
RHF1201
Definitions of specified parameters
Effective resolution bandwidth
For a given sampling rate and clock jitter, the analog input frequency at which the SINAD is reduced of 3 dB.
Pipeline delay
Delay between the initial sample of the analog input and the availability of the corresponding digital data output on the output bus. Also called data latency. It is expressed as a number of clock cycles.
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Package information
RHF1201
9
Package information
Figure 8. SO-48 package
Dimensions Ref. Min. A b c D E E1 E2 E3 e f L P Q S1 12.28 1.30 0.66 0.25 6.22 1.52 2.18 0.20 0.12 15.57 9.52 Millimeters Typ. 2.47 0.254 0.15 15.75 9.65 10.90 6.35 1.65 0.635 0.20 12.58 1.45 0.79 0.43 12.88 1.60 0.92 0.61 0.483 0.051 0.026 0.010 6.48 1.78 0.245 0.060 Max. 2.72 0.30 0.18 15.92 9.78 Min. 0.086 0.008 0.005 0.613 0.375 Inches Typ. 0.097 0.010 0.006 0.620 0.380 0.429 0.250 0.065 0.025 0.008 0.495 0.057 0.031 0.017 0.507 0.063 0.036 0.024 0.255 0.070 Max. 0.107 0.012 0.007 0.627 0.385
16/18
RHF1201
Ordering information
10
Ordering information
Part number RHF1201KSO1 RHF1201KSO2 RHF1201KSO-01V Temperature range -55 C to 125 C -55 C to 125 C -55 C to 125 C Package SO-48 SO-48 SO-48 Marking RHF1201KSO1 RHF1201KSO2 F0521701VXC
11
Revision history
Date 01-Sep-2006 Revision 1 Initial release in new format. Updated failure immune and latchup immune value to 120 MeVChanges
cm2/mg.
29-Jun-2007
2
Updated package mechanical data. Removed reference to non rad-hard components from Section 7.3.2: External reference on page 12.
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RHF1201
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